The present invention relates to a read only memory (which will be shortly referred to as "ROM"), and particularly to a read-out circuit thereof. More particularly, the present invention relates to a memory equipped with a read-out circuit of the type, in which the memorized data of the memory cell of the ROM are read out by detecting whether or not any current flows through that memory cell.
A ROM is divided into (1) an ultraviolet light erasable ROM (which will be shortly referred to as "EPROM": Erasable Programmable ROM), (2) an electrically alterable ROM (which will be shortly referred to as "EAROM": Electrically Alterable ROM), and (3) a PROM (Programmable ROM) such as a fuse ROM or a mask ROM (Mask Programmable ROM).
In a known EAROM, for example, MNOS (structure) type insulated-gate field effect transistors (which will be shortly referred to as "MNOS Tr.") are arranged in the form of a matrix. In this MNOS Tr., electrons and holes are injected by the tunnel effect into the trap at the interface between two kinds of insulating layers (i.e., an Si.sub.3 N.sub.4 layer and an SiO.sub.2 layer) through an SiO.sub.2 layer which is made thinner than the Si side. The MNOS Tr. according to the prior art is shown in section in FIG. 1. In this Figure: reference numeral 11 indicates a silicon (Si) substrate of N-type conductivity; numerals 12 and 13 indicate diffusion layers of P.sup.+ -type conductivity forming the source and drain regions; numeral 14 indicates an SiO.sub.2 layer; numeral 15 indicates an Si.sub.3 N.sub.4 layer; and numeral 16 indicates a gate electrode. By applying a positive writing voltage (about +25 V) to the gate electrode of the MNOS Tr. having the construction thus far described, the electrons are injected into the trap by the tunnel effect so that the threshold voltage of the MNOS Tr. can be lowered (e.g., to about +1 V) to establish the written state (i.e., the conductive state of the MNOS Tr., which will be shortly referred to as "1" state). In order to eliminate this trap of the electrons, the inverse operations are effected by impressing a negative erasing voltage (at about -25 V) upon the gate electrode so that the threshold voltage of the MNOS Tr. can be raised (e.g., to about -8 V) to establish the erased state (i.e., the nonconductive state of the MNOS Tr., which will be shortly referred to as "0" state). In order to detect the difference between the two "0" and "1" states, a reading voltage at about -6 V is impressed upon the gate electrode of the MNOS Tr. so that whether or not any current flows between the source and drain can be sensed.
In a known EPROM, on the other hand, floating-gate type insulated-gate field effect transistors (which will be shortly referred to as "FAMOS Tr.") are arranged in the form of a matrix. A representative of this FAMOS Tr. is shown in FIG. 2. In this Figure: numeral 21 indicates an N type Si substrate; numerals 22 and 23 indicate P.sup.+ -type diffusion layers forming the source and drain regions; numeral 24 indicates an SiO.sub.2 layer; and numeral 25 indicates a floating gate made of polycrystalline Si. In the FAMOS Tr. having the construction thus far described, electrons are injected into the floating gate by effecting the avalanche effect phenomena between the drain and the substrate when a high voltage is impressed between the source and drain so that the writing operation in the "1" state can be effected. In case the reading operation is to be effected, a conductive state is established between the source and drain, when a voltage is impressed inbetween, because an inversion layer is formed inbetween if the floating gate is negatively charged. In other words, the "0" and "1 " states can be judged in accordance with whether the floating gate is negatively charged. The erasure of stored information is accomplished by the exposure of an ultraviolet light to discharge the electrons from the floating gate.
Although the foregoing description is directed to the EAROM and EPROM by way of example, a variety of other ROMs are known in the art.
The aforementioned MNOS Tr. and FAMOS Tr. are exemplified by a P channel type element but can naturally be exemplified by an N channel type element (although the polarity of the voltage to be impressed is inverted).
A read-out circuit having such charactersitics as are suitable for the ROMs thus far described is desired.